The invention pertains generally to semiconductor memory devices. Specifically, the invention pertains to a nonvolatile type ROM (Read Only Memory) composed of a number of memory cells arranged in rows and columns. Yet more particularly, the invention pertains to a ROM of this type which utilizes a floating gate FET for providing a non-volatile storage function. Devices of the general type to which the invention pertains are known as EAROS (Electrically Alterable Read Only Storage) memories.
In an EAROS memory of this general type, charge stored on a floating gate of an FET of each memory cell is used to represent a logic level, that is, a data 1 or 0. When a particular cell of the memory is addressed, the state of the charge on the floating gate determines whether or not the channel of the FET of which the floating gate forms a part is conductive, and hence the amount of current which flows through the selected cell.
A number of techniques are known for transferring charge to and from a floating gate. (As utilized herein, charging of the floating gate is referred to as "programming" and the removal of charge from the floating gate is referred to as "erasing".) In "An Electrically Alterable ROM and It Doesn't Use Nitride", J. W. Kelley et al., Electronics, Dec. 9, 1976, p. 101 ff., there is described a ROM in which programming is achieved using avalanche electron injection and erasing with avalanche hole injection. R. G. Muller et al. in "Electrically Alterable 8192 Bit N-Channel MOS PROM", ISSCC Proceedings, February 1977, p. 188 ff., describe a device utilizing "hot" electron injection for programming and Fowler-Nordheim emission for erasing. U.S. Pat. No. 4,119,995, issued Oct. 10, 1978, to Simko and D. Guterman et al. and "An Electrically Alterable Nonvolatile Memory Cell Using a Floating Gate Structure", IEEE JSSC, April 1979, p. 498 ff., disclose memories utilizing hot electron injection for programming and oxide conduction (tunneling) for erasing. U.S. Pat. No. 4,099,196, issued July 4, 1978, to Simko teaches a memory cell utilizing oxide conduction for both programming and erasing.
All of these approaches suffer from a common drawback in that, in each case, a relatively large negative charge is stored on the floating gate. Due to the negative charge on the floating gate, there is a lower limit to the cell size and hence a limit to the cell density which can be achieved.
To understand this problem, it may be seen that the breakdown voltage B.sub.VN-P of an N.sup.+ P junction of the transistor of a memory cell is determined by: EQU BV.sub.N-P =MV.sub.FG +BV.sub.FG (0).
(See, for instance, Physics and Technology of Semiconductor Devices, A. S. Grove, c. 10, Wiley, November 1967). In this equation, V.sub.FG is the floating gate voltage, M is a constant close to unity, and BV.sub.FG (0) is the zero gate breakdown voltage.
To scale down the size of a device and achieve a desired cell density, the doping levels and junction depths of each transistor of each cell must be correspondingly scaled down thereby resulting in a reduction of the term BV.sub.FG (0). A negative charge transferred to the floating gate during programming causes the term V.sub.FG to be negative. From the above-stated equation, it may readily be appreciated that reducing the term V.sub.FG reduces the maximum allowable voltage that can be applied to the N.sup.+ P junctions and N.sup.+ diffusions of the transistors of the memory cells. Hence, in the memory cells of the prior art memories discussed above, due to the negative charge on the floating gate, a lower limit to the cell size must be imposed so that breakdown does not occur.
Other examples of memory cell structures in which this same problem is present are described in Johnson et al., "16K EE-PROM Relies on Tunneling for Byte Erasable Program Storage", Electronics, Feb. 28, 1980, and in U.S. Pat. No. 4,209,849, issued July 24, 1980 to Schrenk. In the memory cells disclosed therein, a capacitor formed between polysilicon conductors which has a relatively high capacitance compared to the capacitance of a capacitor between the lower polysilicon conductor (which forms a floating gate) and the substrate of the device. Such a high capacitive ratio is necessary to achieve a sufficiently large electric field across the latter capacitor during programming and erasing. The cell size in both cases is limited by the relatively large size of the larger capacitor.
Giebel, "An 8K EEPROM Using the Simos Storage Cell", IEEE JSSC, June 1980, describes a memory cell in which a floating gate is programmed by hot electron injection and erased using FowlerNordheim tunneling through a thin oxide region, similar to the case of the above-mentioned article by Muller et al. This technique requires a considerably high power dissipation during programming and erasing, and hence is considered less desirable than the approach used in the Johnson et al. publication or in U.S. Pat. No. 4,209,849 to Schrenk. Moreover, the technique used by Giebel requires that programming and erasing occur at different positions in the FET gate region of the device. This results in charge carrier trapping at the two separated locations with no opposing fields which would create detrapping, thus making this approach additionally disadvantageous.
Hagiwara et al. in "A 16K bit Electrically Erasable PROM Using N-Channel Si-Gate MNOS Technology", IEEE JSSC, June 1980, describe a nonvolatile memory cell using a metal-nitride-oxide-semiconductor (MNOS) structure (which represents a different technology or technique than the floating gate structures utilized by the present invention and the prior art devices discussed above). In general, the data retention capabilities of an MNOS device are not as good as those of a floating gate device. In addition, it is not possible to fabricate an MNOS device using techniques commonly used for producing standard high speed logic devices. Thus, if it is desired to integrate an MNOS device with a device such as a microprocessor fabricated using standard high speed logic techniques, serious manufacturing problems are encountered.
A non-volatile random access memory fabricated on a single silicon chip is disclosed in "Dual-Electron Injector-Structure Electrically Alterable Read-Only Memory Model Studies", DiMaria et al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, September 1981, and in copending patent application Ser. No. 124,003, filed Feb. 26, 1980, which is assigned in common with the present application. This memory device uses a cell structure composed of an n-channel MOS transistor with DEIS (Dual Electron Injector Stack) material positioned between a control gate and a "floating" polycrystalline silicon gate. Writing is performed by applying a negative voltage to the control gate. This negative voltage causes the injection of electrons from the top silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer. Similarly, erasing is performed by applying a positive voltage to the control gate, which then injects electrons from a bottom silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer.
Other examples of memory cells using a floating gate FET with charge transferred to the floating gate through DEIS material or the like are disclosed in copending U.S. patent application Ser. Nos. 192,579, filed Sept. 30, 1980 now U.S. Pat. No. 4,388,704; 192,580, filed Sept. 30, 1980 now U.S. Pat. No. 4,399,522; and 219,285, filed Dec. 22, 1980 now U.S. Pat. No. 4,363,110.
It is an object of the present invention to provide a memory composed of non-volatile cells which does not suffer from any of the drawbacks enumerated above.
Specifically, it is an object of the invention to provide such a memory device in which the cell size can be reduced beyond that provided by prior art techniques.
Yet further, it is an object of the present invention to provide such a memory cell in which the breakdown voltages are reduced and in which programming and erasing can be achieved utilizing relatively low voltages.